Home > Published Issues > 2014 > Volume 9, No. 11, November 2014 >

A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface

Yujie Zang
School of Information Management, Beijing Information Science & Technology University , Beijing , China,100192
School of Economics and Management, Beihang University, Beijing, China, 100191

Abstract—A fully integrated 3.3 V-to-1.2 V supply voltage regulator for application in IEEE 1394B PHY has been designed in 0.13μm SMIC Mixed Signal process technology. The regulator is able to deliver peak current transient of 300 mA, while the output voltage remain within a margin of 10% around the nominal value. The PSRR response larger than 52 dB for frequencies up to 10 kHz under the condition of IL=300 mA. The FOM of the circuit can be better than 2.5. The circuit can be used in all types of high speed serial data communication system.

Index Terms—On-chip voltage regulator, IEEE 1934B PHY, class-AB.

Cite: Yujie Zang, "A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface," Journal of Communications, vol. 9, no. 11, pp. 876-883, 2014. Doi: 10.12720/jcm.9.11.876-883

PREVIOUS PAPER
LTE Radio Resource Management Conformance Testing: Exploration and Implementation
NEXT PAPER
Low Complexity in Exaggerated Earliest Deadline First Approach for Channel and QoS-aware Scheduler