Abstract—This paper presents an efficient three dimension Networks-on-Chip (NoC) mesh topology which developed for digital image processing. The NoCs are emerging as a good solution for the communication of SoCs. With this advantage there is a significant growth of the number of cores or processing elements in a same chip. Communication between tens or hundreds of cores has become a main issue. We introduce developed 3D mesh topology for resolving this issue that is suitable for digital image processing. A 3D-Mesh is a generic, scalable and configurable topology which uses XYZ Dimension Ordered Routing (DOR) algorithm. We also implement a median filter to restore corrupted digital images. Our method for implementing the median filter is better and preferable compared to the implementation on a 2D mesh architecture. Experimental results show a significant improvement in execution clock cycle count for 3D mesh architecture which gets better while increasing the network size.


Index Terms—3D-Mesh; network-on-chip; core; topology; median filter


Cite: Behzad Davoodnia, Masoom Nazari, Reza Daie Koozekanani, and Mina Zolfy Lighvan, "3D Network-on-Chip Based Median Filter Implementation," Journal of Communications, vol. 13, no. 4, pp. 193-197, 2018. Doi: 10.12720/jcm.13.4.193-197.