Home
Author Guide
Editor Guide
Reviewer Guide
Special Issues
Special Issue Introduction
Special Issues List
Topics
Published Issues
2024
2023
2022
2021
2020
2019
2018
2017
2016
2015
2014
2013
2012
2010
2009
2008
2007
2006
journal menu
Aims and Scope
Editorial Board
Indexing Service
Article Processing Charge
Open Access Policy
Publication Ethics
Digital Preservation Policy
Editorial Process
Subscription
Contact Us
General Information
ISSN:
1796-2021 (Online); 2374-4367 (Print)
Abbreviated Title:
J. Commun.
Frequency:
Monthly
DOI:
10.12720/jcm
Abstracting/Indexing:
Scopus
;
DBLP
;
CrossRef
,
EBSCO
,
Google Scholar
;
CNKI,
etc.
E-mail questions
or comments to
editor@jocm.us
Acceptance Rate:
27%
APC:
800 USD
Average Days to Accept:
88 days
3.4
2023
CiteScore
51st percentile
Powered by
Article Metrics in Dimensions
Editor-in-Chief
Prof. Maode Ma
College of Engineering, Qatar University, Doha, Qatar
I'm very happy and honored to take on the position of editor-in-chief of JCM, which is a high-quality journal with potential and I'll try my every effort to bring JCM to a next level...
[Read More]
What's New
2024-11-25
Vol. 19, No. 11 has been published online!
2024-10-16
Vol. 19, No. 10 has been published online!
2024-08-20
Vol. 19, No. 8 has been published online!
Home
>
Published Issues
>
2019
>
Volume 14, No. 10, October 2019
>
Design of Reconfigurable System-on-Chip Architecture for Optical Wireless Communication
Syifaul Fuada
1
, Trio Adiono
2
, Angga Pratama Putra
2
, Erwin Setiawan
2
1. Universitas Pendidikan Indonesia, Indonesia
2. Institut Teknologi Bandung, Bandung, Indonesia
Abstract
—To meet the growing demands of the data communication infrastructure in the Internet-of-Things era, alternative methods are needed to complement the current technology, one of which employs optics-based communication. In this paper, we develop optical wireless communication (OWC) infrastructure focuses on digital signal processing (DSP) part. We design System-on-Chip (SoC) architecture based on the Orthogonal Frequency-Division Multiplexing (OFDM) technique with reconfigurable hardware resources. The system developed combines ARM microprocessors with FPGAs. For accelerating the digital processing, several essential parts such as Viterbi decoder, FFT, and time synchronizer are applied to the hardware IP (H/W SoC). While the scheduling is carried out on the software (S/W SoC). With this system, the data communication with other devices can be practiced easily, using various peripherals, i.e., Ethernet, UART, and serial-based connection. Afterward, we exploit the system performance in terms of the hardware resources utilization both for DSP Transmitter and DSP Receiver, also the system latency.
Index Terms
—Digital Signal Processing (DSP), Optical Wireless Communication (OWC), OFDM, System-on-Chip (SoC).
Cite: Syifaul Fuada, Trio Adiono, Angga Pratama Putra, and Erwin Setiawan, “Design of Reconfigurable System-on-Chip Architecture for Optical Wireless Communication,” vol. 14, no. 10, pp. 965-970, 2019. Doi: 10.12720/jcm.14.10.965-970.
13-JCM170323
PREVIOUS PAPER
Assessing the Internet of Things Security Risks
NEXT PAPER
The Optimization Potential of Volunteer Computing for Compute or Data Intensive Applications