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General Information
ISSN:
1796-2021 (Online); 2374-4367 (Print)
Abbreviated Title:
J. Commun.
Frequency:
Monthly
DOI:
10.12720/jcm
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Acceptance Rate:
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3.4
2023
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Editor-in-Chief
Prof. Maode Ma
College of Engineering, Qatar University, Doha, Qatar
I'm very happy and honored to take on the position of editor-in-chief of JCM, which is a high-quality journal with potential and I'll try my every effort to bring JCM to a next level...
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2024-10-16
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Volume 17, No. 8, August 2022
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Design of DCO-OFDM System for VLC on Chip at the Register-Transfer Level
Syifaul Fuada
1
, Angga Pratama Putra
2
, and Trio Adiono
3
1. Program Studi Sistem Telekomunikasi, Universitas Pendidikan Indonesia, Bandung, Indonesia
2. VLC Research Group, Pusat Mikroelektronika, Institut Teknologi Bandung, Bandung, Indonesia
3. School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Bandung, Indonesia
Abstract
—This paper reports a System-on-Chip (SoC) architecture design for the DC-biased optical OFDM (DCO-OFDM) Visible Light Communication (VLC) transceiver. The proposed SoC comprises several Digital Signal Processing (DSP) blocks, i.e., Fast Fourier Transform (FFT), Convolutional Encoder (CE), Viterbi Decoder, Quadrature Phase-Shift Keying (QPSK) Modulator/Demodulator, Interleaver/Deinterleaver, and Synchronizer. System was designed through the combination of two Intellectual Property (IP) types: designing IP from the scratch (custom-based IP) and employing available core accelerator IP served by the third party, which is Xilinx library (reuse-based IP). All DSP blocks were targeted for the FPGA development board (Xilinx Zynq SoC 7000), then combined with the ARM microprocessor. In this study, ARM microprocessors were used for various tasks, i.e., scheduling process, on-chip memory as a temporary data storage function, Analog-to-Digital Converter (A/D), Digital-to-Analog Converter (D/A), and Ethernet module as communication medium between SoCs and personal computer (PC). Testing was carried out on the Register Transfer Level (RTL) for hardware (H/W) and software (S/W) models implemented on ARM microprocessors. The system performances were measured through the point-to-point data communication scenarios between a PC transmitter and PC receiver. A 77 kbps of data communication speed and 2.9 ms of data processing latency were obtained using 100 MHz clock speed. The VLC on-chip was successfully demonstrated in RTL phase. This system is suitable for a low-rate communication system application, generally for joint VLC and Internet-things (IoT) technology, (then called as VLC/IoT).
Index Terms
—Visible Light Communication, DCO-OFDM, System-on-Chip, FPGA, Reuse-based Intellectual Property, custom-based Intellectual Property
Cite: Syifaul Fuada, Angga Pratama Putra, and Trio Adiono, "Design of DCO-OFDM System for VLC on Chip at the Register-Transfer Level," Journal of Communications vol. 17, no. 8, pp. 608-624, August 2022. Doi: 10.12720/jcm.17.8.608-624
Copyright © 2022 by the authors. This is an open access article distributed under the Creative Commons Attribution License (
CC BY-NC-ND 4.0
), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.
3-JCM170897
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